1. Field of Invention
This invention relates generally to microprocessor cache systems and specifically to increasing the yield of such systems.
2. Description of Related Art
A cache is a relatively high-speed, small, local memory which is used to provide a local storage for frequently accessed memory locations of a larger, relatively slow, main memory. By storing the information or a copy of the information locally, the cache is able to intercept memory references and handle them directly without transferring the request to the main memory over the system bus. The result is lower traffic on the system bus and decreased memory latencies.
The efficiency of a central processing unit (CPU) depends, in part, upon the hit ratio of requests to cache memory. That is, if requested data is in the cache, there is a cache hit, and the data is readily available from cache memory. Conversely, if the requested data is not in the cache, there is a cache miss, and the data must be retrieved from main memory. In order to increase cache hit ratios, cache memory size has steadily increased over the years, and now may exceed 1 Megabyte for a level-2 (L2) cache.
Unfortunately, as the size of cache memory increases, so does the likelihood of manufacturing defects that render the cache memory unusable, which in turn undesirably decreases manufacturing yield. Previous attempts to combat the loss of manufacturing yield due to unusable portions of cache memory include well-known redundancy and/or mapping techniques. For example, since the L2 cache now typically occupies as much as one-third of the CPU chip, which increases the chances of manufacturing defects in the L2 cache, redundancy rows are built into the cache so that defective cache lines may be mapped to and thereby replaced by the redundancy rows.
However, the mapping of defective rows to redundancy rows requires redundancy features in both the L2 cache address decoders and the L2 cache controller to facilitate such address mappings. These redundancy features undesirably increase circuit complexity and silicon area. Also, when using such redundancy features, the ability to replace defective cache rows is limited by the number of built-in redundant rows and, therefore, if the cache includes more defective rows than redundant rows, the defects cannot be overcome by the redundancy features, and the chip may not be usable.